The IQ-DispML is a multi-layer, fully software configurable display controller IP core. It performs continuous refresh of graphical flat panel displays (TFT LCD, AMOLED) from the designated frame buffers located in a memory device mapped to the system bus.

Multiple layers are blended into a single image, which is outputted to the display. SDRAM and SRAM devices are supported as frame buffers, depending on the bandwidth requirements.

IQ-DispML is designed to provide an optimum tradeoff of performance and resource utilization in FPGA devices while retaining a high degree of configurability. The IP core can be additionally scaled down at compile time by reducing the number of layers, bus widths and fixing timing parameters, allowing the user to fully optimize the IQ-DispML for a specific configuration.

Key feature Set

  • Display and video interface driving
  • Fully programmable
  • Small footprint
  • HD capable

Commercial applications

  • Vending machines
  • Video monitors
  • Automotive infotainment
  • Medical instrumentation
  • Human machine interface (HMI) systems
  • Mobile devices

  • Fully programmable clock and timing control for flat panel displays with progressive scanning
  • Support for resolutions up to 4096x4096
  • Completely variable timing parameters, for standard or specific display resolutions
  • Support for 8,16, 18 or 24 bit RGB output color depth
  • Standard or multiplexed display data bus
  • Display power control lines
  • Interrupt generation on vertical sync for software synchronization
  • Frame buffer management
    • Double buffering to reduce image flicker
    • Variable frame buffer organization with software-configurable memory stripe
    • Image scroll via unconstrained frame buffer addressing
    • Frame buffer color depth support
  • Alpha blending of all layers, with per-layer additional transparency (“layer fading”)
  • Independent positioning and dimensioning of all layers
  • Compile-time configuration for reducing resource cost by fixing parameters
  • Support for multiple clock domains to ease timing closure
  • Integrated DMA memory master supporting low-overhead burst transfers
  • Configuration bus slave interface with address-mapped registers


Block Diagram


Implementation Lattice


FPGA family
ECP3 (ECP3-35EA)
Reg. LUT4s
EBRs Multip. Max. Freq. IO Pins
Light version
(2 layers, 32-bit pipeline)
 3018 4978 4 9 180 MHz * 249 **
Full version
(4 layers, 32-bit pipeline)
5241 8670 6 21 180 MHz * 249**
  Maximum frequency of the system bus interface, for AMBA AHB
  Assuming all core ports routed off-chip



The core has been rigorously tested in functional simulation and actual hardware. The core is accompanied with an automated testbench with a display simulation model and a memory simulation model.

The memory model can be initialized with the desired bitmap through simple software provided with the model

IQ-DispML Data Sheet HOT
  • Created: 2015-05-15
  •   Size: 557.58 KB
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